1. Field of the Invention
This invention relates to computer processors and, more particularly, to page translation in a virtual memory environment.
2. Description of the Related Art
Modem computer systems take advantage of virtual memory to improve performance. For example, in order to make efficient use of memory while taking advantage of the even greater capacity of hard disk storage, processors frequently incorporate a virtual addressing mechanism in which a virtual address may refer to an address space that is much larger than the physical size of memory. The virtual addressing mechanism is commonly performed by a combination of processor hardware and operating system software. In practice, the large virtual address space is usually broken up into pages. Whenever the processor reads or writes to a virtual memory address, specialized processor hardware translates the address into either a physical location on a page (sometimes referred to as a frame) that resides in the physical memory or a reference to a page (or frame) that is stored on disk. If the reference is to a frame stored on disk, the operating system moves that frame into physical memory, swapping out a frame that has not been recently accessed if necessary.
Address translation using paging typically involves a set of data structures known as page translation tables. To translate a virtual address into a physical address, the low-order bits of the virtual address may be mapped directly to the physical address while higher order bits of the virtual address may be used to index into page translation tables to find the higher order bits of the physical address. In a hierarchical page table implementation, a processor may partition the higher order bits of a virtual address into one or more bit-fields, each corresponding to a different level of hierarchy of the page translation tables. Entries in the page translation tables that map virtual addresses to physical addresses may generally be referred to as page table entries (PTEs).
The speed of virtual address translation may be increased by caching PTEs in a CPU cache know as a translation lookaside buffer (TLB). A TLB may have a fixed number of slots for storing PTEs. Since accessing a TLB entry is generally faster than performing an address translation using page translation tables, the size and coverage of the TLB may be an important indicator of overall system performance. Coverage of the TLB depends on the size of the page represented by each TLB entry. Common computer architectures provide only a coarse selection of virtual memory page sizes. For example, the well known x86-64 architecture provides page sizes of 4 KB, 2 MB, and 1 GB. Smaller page sizes reduce the effective capacity of the TLB and increase the miss rate of TLB accesses. Unfortunately, very large pages sizes often result in inefficient allocation of memory for applications that do not require large data sets. In view of the above considerations, systems and methods of improving system performance by improving TLB miss rate and/or increasing TLB effective capacity while maintaining efficient memory usage may be desired.
In addition to the above considerations, while improved TLB miss rate and capacity may provide for certain enhanced capabilities, it may be desirable for processors to be able to continue to run existing software whenever enhanced capabilities are introduced. Accordingly, processor enhancements that continue to support legacy paging modes may be desirable.